//    Copyright (C) 2010 by Dolphin Technology
//    All rights reserved.
// 
//    Copyright Notification
//    No part may be reproduced except as authorized by written permission
// 
//    @file   dti_up_counter.v
//    @par    Company:
//              Dolphin Technology
//    @par    Project:
//              [projectname]
//    @par    Author:
//              N. Huy Bui
//    @par    Date:
//              July 17, 2012
//    @brieft
//              [a brieft description of the module]
//$Id$

module dti_up_counter (pop_clk, pop_rst_n, pop_req_n, fifo_empty, count_out);

parameter 	  IN_WIDTH    = 24;
parameter 	  OUT_WIDTH   = 8;
parameter 	  BYTE_ORDER  = 1; 		//0: big-endian, 1: little-endian
parameter 	  K 	      = IN_WIDTH/OUT_WIDTH;
parameter 	  COUNT_WIDTH = $clog2 (K);

input 		  pop_clk; 			//clock signal
input 		  pop_rst_n;
input 		  pop_req_n;
input 		  fifo_empty;
output reg [COUNT_WIDTH-1:0] count_out;
reg 	  [COUNT_WIDTH-1:0] count_next;

always @ (posedge pop_clk or pop_rst_n)
begin
  if (!pop_rst_n)
    count_out <= 0;
  else
    count_out <= count_next;
end

always @ (pop_req_n or fifo_empty or count_out)
begin
  if (fifo_empty)
    count_out = K;
  else if (!pop_req_n)
    count_next = (count_out == K-1) ? 0 : count_out + 1;
  else
    count_next = count_out;
end

endmodule // dti_up_counter

